This invention relates to power switching circuits. More specifically, the invention relates to a snubber circuit in a power switching circuit which enables improved operating efficiencies.
Conventional power inverters provide a pair of power transistor switches connected in series between positive and negative DC terminals which operate during opposite half cycles to provide an AC output. The wire leads between components, however, create parasitic inductances which increase voltage spikes across the power transistor switches. As a result, snubber circuits are used to reduce the affect of these parasitic inductances and to also reduce switching losses in the power transistor switches.
An example of a conventional snubber circuit is a circuit having a parallel connection of a resistor and a diode connected in series with a capacitor, and which circuit is connected across the collector and emitter of each power transistor connected in series between the positive and negative terminals. The capacitor is charged by a circuit spike resulting from the parasitic inductances. The capacitor discharges through the resistor when the power transistor is turned on. The conventional snubber circuit results in high power losses since the snubber circuit remains active throughout the output frequency cycle period. This results in high snubber circuit losses.
A snubber circuit for a power inverter which provides high efficiency inverter operation is therefore needed.